Search results for "Parasitic capacitance"
showing 5 items of 5 documents
A DC and small signal AC model for organic thin film transistors including contact effects and non quasi static regime
2017
Abstract We present a compact model for the DC and small signal AC analysis of Organic Thin Film Transistors (OTFTs). The DC part of the model assumes that the electrical current injected in the OTFT is limited by the presence of a metal/organic semiconductor junction that, at source, acts as a reverse biased Schottky junction. By including this junction, modeled as a reverse biased gated diode at source, the DC model is able to reproduce the scaling of the electrical characteristics even for short channel devices. The small signal AC part of the model uses a transmission line approach in order to compute the impedances of the channel and parasitic regions of the device. The overlap capacit…
On the design of a multiple-output DC/DC converter for the PHI experiment on-board of solar orbiter
2013
Power converters for experiments that have to fly on board space missions (satellite, launchers, etc.) have very stringent requirements due to its use in a very harsh environment. The selection of a suitable topology is therefore not only based on standard requirements but additional more strict ones have also to be fulfilled. This work shows the design procedure followed to build the Power Converter Module (PCM) for the Polarimetric and Helioseismic Imager (SO/PHI), experiment on board the Solar Orbiter Satellite. The selected topology has been a Push-Pull, for a power level of approximately 35 W and with seven output voltages. Galvanic isolation is needed from primary to secondary, but no…
A cylindrical GEM detector with analog readout for the BESIII experiment
2016
Abstract A cylindrical GEM detector with analog readout is under development for the upgrade of the Inner Tracker of the BESIII experiment at IHEP (Beijing). The new detector will match the requirements for momentum resolution ( σ pt / p t ~ 0.5 % at 1 GeV) and radial resolution ( σ xy ~ 120 μ m ) of the existing drift chamber and will improve significantly the spatial resolution along the beam direction ( σ z ~ 150 μ m ) with very small material budget (less than 1.5% of X 0 ). With respect to the state of the art the following innovations will be deployed: a lighter mechanical structure based on Rohacell, a new XV anode readout plane with jagged strip layout to reduce the parasitic capaci…
Design of MOS Current Mode Logic Gates – Computing the Limits of Voltage Swing and Bias Current
2005
Minimizing a quality metric for an MCML gate, such as power-delay product or energy-delay product, requires solving a system of nonlinear equations subject to constraints on both bias current and voltage swing. In this paper, we will show that the limits of the swing and the bias current are affected by the constraints on maximum area and maximum delay. Moreover, methods for computing such limits are presented.
A Design Methodology for Low-Power MCML Ring Oscillators
2007
In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.